1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit inputting a data input signal.
2. Description of the Related Art
FIG. 6 is a time chart showing three types of signals outputted by testing equipment to a semiconductor integrated circuit. The testing equipment can output three types of signals, namely a Non-Return to Zero signal, a Return to Zero signal and a short-pulse signal. Cycle times T1, T3, T4 show a signal indicating data of “1”, respectively. The cycle time T2 shows a signal indicating data of “0 (zero)”. The Non-Return to Zero signal changes once in each of the cycle times T1, T2, T3 being cycle times in which data changes. The Return to Zero signals change twice in each of the cycles T1, T3, T4 indicating the data of “1”. The short-pulse signal is generated by combining (exclusive OR operation) the two Return to Zero signals having mutually different phase.
FIG. 7 is a circuit diagram showing input circuits 111 and an internal logic circuit 103 in the semiconductor integrated circuit. Via n-pieces of the input circuits 111, n-bits of data input signals IN1 to INn are inputted into data input terminals of n-pieces of flip-flops 131 in the internal logic circuit 103, respectively. A clock signal CLK is inputted into clock terminals of the n-pieces of flip-flops 131 via an input circuit 121.
When testing the input circuits 111 and the input circuit 121, the data input signals IN1 to INn and the clock signal CLK are inputted from the testing equipment. At that time, as shown in FIG. 8, as data input signals IN1 to INn, the Non-Return to Zero signals are used and, as a clock signal CLK, the Return to Zero signal is used. However, along with recent increase in speed in the semiconductor integrated circuits, the pulse width at practical use is becoming shorter than that of the Non-Return to Zero signal that a general testing equipment can generate, requiring the test to be performed by inputting the data input signals IN1 to INn having a shorter pulse width.
FIG. 8 is a timing chart showing an example of the data input signals IN1 to INn and the clock signal CLK. When the semiconductor integrated circuit inputs the clock signal CLK and the data input signals IN1 to INn, a rule called a setup time TS and a holdtime TH has to be observed. For instance, the flip-flops 131 latch to memorize the data input signals IN1 to INn in synchronization with a rising edge of the clock signal CLK. At this time, the setup time TS is a time period in which the data of the data input signals IN1 to INn has to be fixed before the rising of the clock signal CLK. The holdtime TH is a time period in which the data of the data input signals IN1 to INn has to be fixed after the rising of the clock signal CLK. However, the data input signals IN1 to INn that the general testing equipment outputs have a very large phase variation (skew) TT, in which the data input signals IN1 to INn themselves also have a large phase variation mutually, making it difficult to observe the rule of the setup time TS and the holdtime TH. Therefore, it is difficult to test the semiconductor integrated circuit inputting the data input signals IN1 to INn having the short pulse width.
FIG. 9 is a circuit diagram of the semiconductor integrated circuit having signal generation circuits 901 for the test, which has the signal generation circuits 901 and selectors 902 in addition to FIG. 7. The signal generation circuit 901 generates and outputs the data input signal based on the clock signal outputted by the input circuit 121. The selector 902 selects either the data input signal of the input circuit 111 or that of the signal generation circuit 901 to output the selected data input signal to the data input terminal of the flip-flop 131. Since the signal generation circuits 901 in the semiconductor integrated circuit generate the data input signals, the data input signals having a small phase variation are generated, so that the test of the semiconductor integrated circuit can be performed. However, in this method, the test of the data input signals having a small phase variation cannot be performed to the input circuit 111.
Further, in Japanese Patent Application Laid-Open No. Sho59-116064 (Patent document 1), there is described equipment testing a logic circuit by comparing data stored in a shift register incorporated in the logic circuit and an expectation value data.
Furthermore, in Japanese Patent Application Laid-Open No. Sho62-115857 (Patent document 2), there is described a semiconductor integrated circuit device including: an input terminal inputting a serial signal corresponding to each test mode, a serial-parallel converter circuit connected to the input terminal, and a test mode setting circuit connected to the serial-parallel converter circuit and having a decoder decoding a converted parallel output.
As described above, it is difficult for the testing equipment to output the data input signal having a small phase variation. Further, even if the semiconductor integrated circuit generates the data input signal internally, it is impossible to test the input circuit with the data input signal. Specifically, it is difficult to test the input circuit inside the semiconductor integrated circuit inputting the data input signal having the short pulse width.